caching - Assuming direct-mapping cache, how is LDR handled in the following cases? -


i've been tasked make "timing" table following code (using 5-stage pipeline):

ldr r1, = 0x345678 ldr r2, [r1] ldr r3, =0xfc167b ldr r4, [r3] ldr r5, =0xd8967a ldr r6, [r5]

assuming these "cache misses", wondering delays introduced if assuming 1-cycle penalty in event of miss. thoughts first line, ldr r1, = 0x345678, wouldn't cause penalty, since loading word register.

but second line, ldr r2, [r1], thinking there will penalty, since trying read cache, isn't in cache. hence, there delay after "memory" stage of pipeline?

regards


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