makefile - C++ make specific target -

i want make specific executable file designate target. create sample project below

./main_a.cpp ./main_b.cpp ./include ./include/fun.h ./src ./src/fun.cpp ./makefile 

main_a.cpp

#include "fun.h"  #include <stdio.h>  int main(int argc, char **argv) {     fun();     printf("aaa\n"); } 

main_b.cpp

#include "fun.h"  #include <stdio.h>  int main(int argc, char **argv) {     fun();     printf("bbb\n"); } 

fun.h

#include <stdio.h>  extern void fun(); 

fun.cpp

#include "fun.h"  void fun() {     printf("test "); } 

the content of makefile listed blow

objdir := obj/ srcdir := obj/src  cxx_include = -i. -i ./include  cxx_srcs := $(shell find src/ -name "*.cpp")  cxx_objs = $(addprefix $(objdir), ${cxx_srcs:.cpp=.o})  exe_aa = main_a exe_bb = main_b  aa: $(objdir) aa: $(srcdir) aa: cxx_srcs += main_a.cpp  # take main_a.cpp main aa: $(exe_aa)  bb: $(objdir) bb: $(srcdir) bb: cxx_srcs += main_b.cpp  # take main_b.cpp main bb: $(exe_bb)  $(exe_aa): $(cxx_objs)     @echo "building aaa :"     $(cxx) $(cxx_objs) -o $@      @echo "building finished:"   $(exe_bb): $(cxx_objs)     @echo "building bbb :"     $(cxx) $(cxx_objs) -o $@      @echo "building finished:"  $(objdir)%.o: %.cpp $(deps)     $(cxx) $(cxx_include) -c $^ -o $@  $(srcdir):     mkdir -p $(srcdir)  $(objdir):     mkdir -p $(objdir)  .phony: clean  clean:     rm -rf $(objdir) $(exe_aa) $(exe_bb) 

what want if run make aa, generate make_a errors occurred show below:

mkdir -p obj/ mkdir -p obj/src g++ -i. -i ./include -c src/fun.cpp -o obj/src/fun.o building aaa : g++ obj/src/fun.o obj/main_a.o -o main_a  g++: error: obj/main_a.o: no such file or directory makefile:24: recipe target 'main_a' failed make: *** [main_a] error 1 

same errors raised when run make bb

how should modify makefile can generate specific executable file designate target, thanks

your problem that, stated in the gnu make manual, target-specific variables available inside recipe of rule. not available in prerequisite list of rule.

so in situation:

$(exe_aa): $(cxx_objs)         @echo "building aaa :"         $(cxx) $(cxx_objs) -o $@          @echo "building finished:" 

the version of cxx_objs in prerequisites list doesn't see new value added target-specific variable:

aa: cxx_srcs += main_a.cpp 

and make doesn't know needs build object file. cxx_objs value in recipe does see new value target-specific variable, , tries link object file doesn't exist. if changed linker rule more "correct", this:

$(exe_aa): $(cxx_objs)         @echo "building aaa :"         $(cxx) $^ -o $@          @echo "building finished:" 

then you'd see problem, because link line wouldn't contain object either.

eta

there lots of possible ways this. 1 list object file directly , not use target-specific variables @ all:

$(exe_aa): $(obj_dir)main_a.o $(cxx_objs)         @echo "building aaa :"         $(cxx) $^ -o $@          @echo "building finished:" 

another use secondary expansion:

.secondexpansion: $(exe_aa): $$(cxx_objs)         @echo "building aaa :"         $(cxx) $^ -o $@          @echo "building finished:" 

(note double-dollar sign in prerequisite list). use generated include files, recursive makefiles, or eval.