cpu architecture - When accessing memory, will the page table accessed/dirty bit be set under a cache hit situation? -


as far know, memory access of cpu involves cpu cache , mmu. cpu try find target in cache , if cache miss happens, cpu turn mmu. during accessing mmu, accessed/dirty bit of correspondent page table entry set hardware.

however best of knowledge, cpu design won't trigger mmu unless there's cache miss, , here problem is, accessed/dirty bit of page table entry still set under cache hit? or it's architecture related?

most caches virtually indexed , physically tagged, faster access. cpu issues virtual address , index bits of address used locate entry. during time address sent tlb getting physical address. time cache has located entry, tlb return physical address used tag comparison. no 2 things can happen.

  1. tlb not have entry (tlb miss)
  2. cache tag mismatch (cache miss)

in case of 1, need access page table entry (pte) correct physical address.

in case of 2, if tlb has returned valid mapping, need fetch it. if tlb alss has miss (i.e, 1 , 2), need physical address pte , fetch data.

so answer question, in case of hit, pte doesnot need know all.


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